Method for manufacturing a non-volatile memory, non-volatile memory device, and an integrated circuit

ABSTRACT

A method of manufacturing a non-volatile memory device, including providing at least one control gate layer on a substrate. A passage may be created between the at least one control gate layer and the substrate. In the passage at least one filling layer may be provided. A floating gate structure including the filling layer may be formed, as well as a control gate structure including the at least one control gate layer, the control gate structure being in a stacked configuration with the floating gate structure.

FIELD OF THE INVENTION

This invention relates to a method for manufacturing a non-volatilememory, to a non-volatile memory device, and to an integrated circuit.

BACKGROUND OF THE INVENTION

Non-volatile memory, such as electrically erasable programmable readonly memory (EEPROM) or flash memory, typically includes an arrangementof floating gate field effect transistors (FG-FET). The FG-FET includesa floating gate which is electrically isolated, creating a floatingnode, but which is capacitively connected to the channel of the fieldeffect transistor. The FG-FET further has a control gate in a stackedarrangement with the floating gate. The control gate is positioned abovethe floating gate and is electrically isolated from the floating gate,but in capacitive contact with the floating gate. The charge in thefloating gate, and hence the voltage thereof can be controlled by meansof the control gate.

The arrangement of FG-FET is typically manufactured by providing apolycrystalline or amorphous dielectric layer on a crystalline substrateand depositing a floating gate layer of polycrystalline silicon on thedielectric layer. On the floating gate layer a control gate layer isdeposited after a second dielectric layer is deposited, which separatesthe floating gate layer and the control gate layer. Typically, inconventional technology a dielectric layer of SiO₂ or a tri-layer ofSiO₂/Si₃N₄/SiO₂ (so called oxide-nitride-oxide or ONO layer) isdeposited in order to obtain a high quality dielectric between thefloating and the control gate.

However, a disadvantage of this process is that the characteristics ofthe floating gate layer, the second dielectric layer and the controlgate layer cannot be controlled as accurately as would be desirablebecause they are deposited on a polycrystalline or amorphous layer. Forexample, the deposited dielectric layers have a relatively high densityof defects and charge carrier traps both in the bulk of the dielectricmaterial and at the interfaces. These defective sites might captureelectrons, holes or even ionic contaminants that would distort theoperation of the memory cell or make the distinction in reading betweenstored values very difficult if not impossible. Also,

SUMMARY OF THE INVENTION

The present invention provides relates a method for manufacturing anon-volatile memory, a non-volatile memory device, and an integratedcircuit as described in the accompanying claims.

Specific embodiments of the invention are set forth in the dependentclaims.

These and other aspects of the invention will be apparent from andelucidated with reference to the embodiments described hereinafter.

BRIEF DESCRIPTION OF THE DRAWINGS

Further details, aspects and embodiments of the invention will bedescribed, by way of example only, with reference to the drawings.

FIGS. 1A-D schematically shows cross-sectional views of a non-volatilememory device in different stages of a first example of a method ofmanufacturing a non-volatile memory device.

FIGS. 2A-G schematically shows perspective, opened views of anon-volatile memory device in different stages of a second example of amethod of manufacturing a non-volatile memory device.

FIGS. 3A-G schematically shows cross-sectional views of the example FIG.2A-G, taken along the lines II-II in FIG. 2A-G.

FIG. 4 schematically shows a cross-sectional view of a non-volatilememory device in a stage of a third example of a method of manufacturinga non-volatile memory device.

FIGS. 5A-E schematically shows cross-sectional views of a non-volatilememory device in different stages of a fourth example of a method ofmanufacturing a non-volatile memory device.

FIGS. 6A-E schematically shows cross-sectional views of a non-volatilememory device in different stages of a fifth example of a method ofmanufacturing a non-volatile memory device.

FIG. 7 schematically shows a cross-sectional view of an example of anembodiment of an integrated circuit.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

Referring to FIG. 1, a first example of a method of manufacturing anon-volatile memory device is illustrated therein. In the shown example,a non-volatile memory 100, for example flash memory or ElectricallyErasable Programmable Read Only Memory (EEPROM), is formed on asubstrate 1.

As illustrated in FIG. 1A, for example, one or more control gate layers4 may be provided on one or more layers of a substrate 1. In the shownexample, the substrate 1 is a mono-crystalline, monolayer substrate 1.However, the substrate 1 may alternatively include two or more layersand/or be polycrystalline or be amorphous.

The control gate layer 4 may be made of any suitable material, such aspolycrystalline silicon, from hereon referred to as polysilicon,mono-crystalline silicon or a metal, and be provided using any suitabletechnique, for example by (vapour) deposition. The control gate layer 4may be provided directly on the substrate 1. Alternatively, the controlgate layer 4 may be deposited on top intermediate layers present betweenthe control gate layers 4 and the substrate 1, as e.g. explained belowwith reference to FIGS. 2 and 4. The control gate layer 4 may forexample be a mono-crystalline grown on top of an epitaxial sacrificiallayer such as SiGe on a silicon substrate.

As shown in FIG. 1C, a space 10 may be provided between the control gatelayers 4 and the substrate 1. In this respect, from hereon, the space 10will be referred to as being situated below the control gate layer(s) 4.However, the terms “below,” “above,” “top,” “bottom,” “over,” “under”and the like in the description and in the claims, if any, are used fordescriptive purposes and not necessarily for describing permanentrelative positions. It is understood that the terms so used areinterchangeable under appropriate circumstances such that the examplesdescribed herein are, for example, capable of operation in otherorientations than those illustrated or otherwise described herein.

The space 10 may be created in any manner suitable for the specificimplementation. For example, as explained below in more detail withreference to FIGS. 2 and 4, one or more sacrificial layers 2 may bepresent between the control gate layer 4 and the substrate 1. Thesacrificial layer 2 may then be removed in the area(s) below the controlgate layer 4 where the floating gate structure 120 is to be provided,for example be selective etching or another suitable process. Also, forexample, the control gate layer 4 may be partially removed at the sidefacing the substrate 1 and/or the substrate 1 may be partially removedat the side facing the control gate layer 4 in order to create the space10.

The space 10 may be filled with any material suitable to create afloating gate structure 120 in any manner suitable for the specificimplementation. For example, one or more layers 6,7 may be provided inthe space 10, as shown in FIG. 1D. Thus, the layer(s) 6,7 can be formedon the layers of the substrate 1 and of the control gate layer 4 andhence, at least partly, from a crystalline base. Accordingly, theformation of the layers 6-7 can be controlled accurately. As shown inFIG. 1D, for example, a stack of layers 6,7 may be provided in the space10. As explained below in more detail, the stack may include one or moreof: a control gate dielectric layer, a floating gate layer, a floatinggate dielectric layer.

For example, in the space 10 a conducting layer 7, from hereon referredto as the floating gate layer, may be provided between the control gatelayer 4 and the substrate 1. The floating gate layer 7 may for examplebe formed into the actual floating gate. The floating gate layer 7 mayfor example be made of polysilicon and for example be formed usingvapour deposition or another suitable technique. The floating gate layer7, such as a layer of polysilicon or a metal, may for example beprovided between the dielectric layers 6 on the walls 11,12.

Also, for instance, a top dielectric layer 6 may be provided in thespace 10 between the control gate layer 4 and the floating gate layer 7.The top dielectric layer 6, from hereon referred to as the control gatedielectric layer, may electrically insulate the control gate layer 4from the floating gate layer 7 when no control voltage is applied to thecontrol gate layer 4 but allow charge carriers to pass from or to thefloating gate layer 7 if a sufficiently strong control voltage isapplied on the control gate layer 4, e.g. by mechanisms such astunneling or hot carrier injection. Thereby, charge may be stored in thefloating gate 120 or be removed from the floating gate 120 when applyinga suitable voltage, whereas the charge in the floating gate 120 willremain the same when no voltage is applied to the control gate 110. Thecontrol gate dielectric layer 6 may for example be formed between thecontrol gate structure 110 and the floating gate structure 120 byproviding a dielectric material on a control gate side wall 11, whichdefines the space 10 at a control gate side.

In the space 10, a bottom dielectric layer 6 may for example be providedbetween the floating gate layer 7 and the substrate 1. A floating gatedielectric 6 which electrically isolates the floating gate structurefrom the channel of the non-volatile memory device 100 may be formed byproviding a dielectric material on the channel side wall 12 of the space10 which defines the space 10 at a channel side. The floating gatedielectric layer 6 may electrically insulate the floating gate layer 7from the substrate 1, but enable a capacitive contact between thefloating gate layer 7 and the channel 115. Thereby, the voltage in thefloating gate layer 7 (caused by the charge present in the floating gatelayer 7) can control the flow of charge carriers through the channel115. As shown in FIG. 1E, below the bottom dielectric layer 6, fromhereon referred to as the floating gate dielectric, a channel 115 may beprovided which connects a source and drains 113,114. The channel 115 mayfor example be provided in the substrate 1, e.g. by providing a suitabledoping profile, or be provided on top of the substrate 1.

The dielectric layers may be provided in any manner suitable for thespecific implementation. For example, as shown in FIG. 1D, walls 11,12of the space 10 may be provided with a dielectric layer 6. In thisexample, the walls 11,12 extend parallel to the surface of thesubstrate, and hence by providing a dielectric layer, the inside of thespace 10 (which may further in the process be (partially) filled withthe floating gate layer 7) can be electrically respectively insulatedfrom the substrate 1 and the control gate layer 4 in a simple manner.The dielectric layer 6 may for example be a silicon-oxide or a high-kdielectric. The dielectric layer 6 may for example be obtained byoxidization of the walls 11,12 (e.g. when the walls 11,12 are made of(polycrystalline or crystalline)silicon) or by atomic layer deposition(ALD) of the desired dielectric material. The dielectric material mayfor example be one or more layers of HfO₂, ZrO₂, HfZrO_(x), HfSiON,Ta₂O₅, Al₂O₃ and the like. After formation of the dielectric layer(s),the floating gate layer 7 may be formed. The oxidization may for examplebe a thermal oxidation of a crystalline silicon.

The formation of the non-volatile memory 100 on the substrate 1 mayinclude forming, from the substrate and the provided layers, one or morefloating gate structures 120 and one or more control gate structure 110in a stacked configuration with one or more of the floating gatestructures. As illustrated in FIG. 1E source and drain 113,114 and achannel 115 may also be provided, in order to obtain a non-volatilememory device 100.

The gate structures 110,120 may be formed in any manner suitable for thespecific implementation. As illustrated in FIGS. 1A and 1B, for examplethe control gate layers 4 may be patterned prior to the formation of aspace 10 below the control gate layer 4 in order to shape the controlgate layer 4 into a control gate structure 110. The control layer 4 mayfor example be a continuous layer deposited over substantially the wholesubstrate 1, as shown in FIG. 1A. The continuous layer may be patternedby removing the control gate layer 4 completely outside the areas inwhich the control gate structure 110 is to be provided, as shown in FIG.1B. For instance, a patterned protective layer 5, such as a hardmask,may be provided which covers part(s) of a top surface 40. The bare partsof the top surface 40 may then be exposed to a medium suitable to removethe control gate layer 4 but which leaves the material covered by theprotective layer 5 intact. The medium may for example be an etchant,e.g. an anisotropic etchant, such as a wet etchant or a dry etchant.

If present, one or more of the intermediate layers 2,3 may be patternedas well, as illustrated in FIG. 2C. The intermediate layers 2,3 may forexample be provided with the same pattern as the control gate layer 4,and may be patterned simultaneously with the control gate layer 4. Forexample, all the intermediate layers 2,3 between the control gate layer4 and the substrate 1 may be patterned. The intermediate layers 2,3 mayfor example be completely removed outside the areas where the floatinggate structure 120 is to be provided.

As illustrated in FIGS. 1D and 1E, the floating gate structure 120 mayfor example be formed during the formation of the layer(s) in the space10. However, it is also possible that the floating gate structure 120 isformed after the desired layers are provided in the space 10. Forexample, one or more of the layers 6,7 may be a continuous layer whichextends outside the space 10 and of which the parts outside the space 10are removed to form the floating gate structure 120.

In the examples of FIGS. 2A-3G, 5A-E and 6A-E, the figures with index Aand B correspond to the phase shown in FIGS. 1A and B, and for sake ofbrevity are not described in full detail.

As shown in the figures with index A, one or more intermediate layers2,3 may be present between the substrate 1 and the control gate layer 4.The control layer 4 may for example be provided on a multi-layerstructure which includes the substrate 1 and one or more intermediatelayers, such as a sacrificial layer 2. In the examples of FIGS. 2-6, theintermediate layers also include a top intermediate layer 3 whichseparates the sacrificial layer 2 from the control gate layer 4. Thesacrificial layer 2 is provided between the substrate 1 and the topintermediate layer 3.

The sacrificial layer 2 and top intermediate layer 3 may for example becrystalline layers grown on a (mono)crystalline substrate 1, for exampleusing epitaxial techniques. The sacrificial layer 2 may for example be aSiGe epitaxial layer grown on a substrate of monocrystalline silicon.The top intermediate layer may for example be a Si or SiGeC (e.g. with aCarbon content between 0.5%-3.0%) layer. For example, the sacrificiallayer 2 may be a SiGe layer with a Ge content of 5% to 50%. Thesacrificial layer 2 may for example have a thickness of 50 Angstrom ormore and/or 500 Angstrom or less A. The top intermediate layer 3 may forexample be a silicon epitaxial layer, and for instance have a thicknessin the range of 40 Angstrom or more and/or 500 Angstrom or less.

The space 10 may be provided between the control gate layer 4 and thesubstrate 1 in any layer suitable for the specific implementation. Asillustrated in FIG. 2D-3D,5D,6D the space 10 may be created below thecontrol gate layer 4, for example by removing the sacrificial layer 2,e.g. by etching with a suitable etchant. As shown in FIGS. 2D and 3D,the removal may be selective to the sacrificial layer 2, i.e. the topintermediate layer 3 and/or the substrate 1 may be left intact. Thereby,the walls 11,12 of the space 10 may be made from mono-crystallinematerials and hence layers formed on or from the top intermediate layer3 and the substrate 1 are formed on or from a mono-crystalline layer andmay therefore have a good quality in that a low amount of defects,traps, interface states and scattering centres may be obtained. Thesacrificial layer 2 may for example be removed by exposing the layer toan etchant which is selective for the material of the sacrificial layer.The etchant may for example be a chemical dry etchant. A suitableetchant for selectively removing SiGe in a Si/SiGe multilayer has foundto be Shibaura CDE-80 manufactured by SHIBAURA, Zama-Shi, Japan.However, other suitable etchants or processes may likewise be used.

The space 10 may for instance be created such that one or more otherlayers are present between the layer(s) in which the space is providedand the control gate layer 4.

As shown in the example of FIGS. 2D and 3D, for instance, the topintermediate layer 3 may abut to the control gate layer 4 and form thecontrol gate side wall of the space 10. As shown in FIGS. 5C and 6C, forinstance, the top intermediate layer 3 may be adjacent, but notabutting, to the control gate layer 4. For example, a dielectric layer40 may be present between the control gate layer 4 and the topintermediate layer 3 before formation of the space 10. The dielectriclayer 40 may for example be made of siliconoxide or other suitable gatedielectric material.

As illustrated in FIGS. 2E and 2F one or more dielectric layers 6 and/orfloating gate layers 7 may be provided in the space 10. For example, thelayers 6,7 may be provided in an orientation parallel to a longitudinaldirection of the space 10. The material layers 6,7 in the space 10 maybe provided in any manner suitable for the specific implementation.

For instance, in the example of FIGS. 2 and 3, the top intermediatelayer 3 (which abuts to the control gate layer 4 in this example) may,be provided with or converted into a dielectric layer at the interfacewith the space 10, as shown in FIGS. 2E and 3E. Thus, the control gatedielectric can be formed.

In case the top intermediate layer 3 (and the substrate 1) are made ofsilicon, the silicon may for instance be oxidised in order to provide adielectric layer 6 on the walls 11,12 of the space 10. For instance, asillustrated in FIG. 2E, after providing the space 10, e.g. in thisexample after etching the sacrificial layer 2, exposed surfaces may besubjected to an oxidation treatment. For example, the walls 11,12 of thespace 10 and the side walls 111,112 of the control gate layer 4 may beoxidised. An oxide layer, e.g. siliconoxide, of e.g. about XX micron maybe formed on the longitudinal walls of the space 10. In case thesubstrate 1 and/or the top intermediate layer 3 and/or the control gatestructure are made from silicon, the exposed surfaces may be subjectedto a dry or wet oxidation. For example, a dry oxidation may be peformedby exposing the surfaces to O₂ gas with, optionally admixtures of N₂ fordilution and incorporation of nitrogen and/or HCL for enhanced reactionrate. The O₂ may be introduced into the chamber at atmospheric pressuresat a temperature in the range between 900° C. and 1150° C. A wetoxidation may be for example be employed by exposing the surfaces towater vapour or H₂ and O₂ at atmospheric pressures

As an alternative or in addition to the oxide dielectric, another typeof dielectric layer may be formed on the exposed surfaces of the walls11,12 of the space 10, for example by a suitable chemical reaction ofthe material of the top and bottom wall 11,12. For example, a high-Kdielectric layer may be formed by HfO₂, ZrO₂, HfZrO_(x), Ta₂O₅, Al₂O₃ orother suitable materials. After formation of the dielectric layers 6, afloating gate layer 7 may be provided by Chemical Vapour Deposition(CVD), metal-organic CVD (MOCVD) or by ALD in at least a part of theremaining space 10, as is shown in FIG. 2F. The floating gate layer 7may, for example, be a layer of polysilicon, SiGe (, for example with aGe content between 5%-50% in case the SiGe is a a sacrificial layer orbetween 0% and 100% in case the SiGe is a filling layer. or othersuitable gate materials such as metals or silicides: TiN, TaC, TaN, WN,TiN, NiSi, CoSi, PtSi, ErSi or other suitable materials.

As illustrated in 5D, for example the entire top intermediate layer 3may be converted into a control gate dielectric, e.g. by oxidization.Thereby, the converted intermediate layer 3 forms the control gatedielectric together with the dielectric layer 40. Accordingly, thedielectric layers 6 may be formed independent from each other, whereasin the example of FIGS. 2A-3G, the dielectric layer separating thefloating gate layer 7 from the control gate layer 4 and the dielectriclayer separating the floating gate layer 7 from the substrate 1 arecreated simultaneously. As illustrated in FIG. 5E, the space between thedielectric layers 6 may then be provided with a floating gate layer 7.

Alternatively, as illustrated in FIG. 6D, the top intermediate layer 3may only be partially converted or be coated with a dielectric layer. Incase the top intermediate layer 3 is a conducting layer (or convertedinto a conducting layer) and separated from the control gate layer 4 bya dielectric layer 40, the top intermediate layer 3 may form a floatinggate layer, and as shown in FIG. 6D be provided at the interface withthe space 10 with a dielectric layer 6. The dielectric layer may fillthe space 10 or, as shown in FIG. 6D, form a thin layer with a thicknessless than the distance between the walls 11,12, after which the space 10is filled with a dielectric filling material, such as a high-Kdielectric 6′, as shown in FIG. 6E. Thereby, a multi-layer floating gatedielectric is obtained. Thereby, the physical thickness of thedielectric layer may be relatively thin while the effective dielectricconstant may be relatively high compared to the thickness.

The space 10 may be filled in any manner suitable for the specificimplementation. For example, the space 10 may be partially filled,leaving an non-filled, closed off, cavity 72 in the space 10. Referringto FIG. 4, for example, the space 10 may be filled by introducing afilling material at one or more of the opening(s) of the space 10. Thefilling material may partially fill the space and close of the openingsin regions 70,71, leaving a region 72 in the space 10 which is notfilled (but may e.g. be filled with the same medium that surrounds thedevice 110, such as air or other (mixtures) of gas(ses)). Thus, thefloating gate layer 7 may have a different composition in differentregions of the space 10, and for example have be conducting in regions70,71 while electrically insulating in regions 72 which separate theconducting regions 70,71. The conducting regions 70,71 may for examplebe different charge trapping areas, thus allowing multiple values to bestored in the non-volatile memory device. The region 72 is created bypinching-off the tunnel at both ends by using a high CVD depositionrate. So the space 72 is more or less an air gap.

As illustrated in FIGS. 2G,3G,5E, and 6E after the space 10 is filled,the non-volatile memory device 100 may be completed, for example byproviding source 113 and drains 114. For instance, source and draincontacts 113,114 may be provided which are connected via a channel 115and the channel 115 may be capacitive contact with the floating gatestructure. Also, an electrically isolating layer 8 may be provided whichcovers the side walls 111,112 of the stacked configuration. For examplespacers 8, for example nitride spacers, or other protective layers maybe provided at the side walls of the stacked configuration, in order toprotect and/or isolate the non-volatile memory device 100 from, forexample, layers provided during further manufacturing.

The outside of the non-volatile memory device 100 may be provided with aprotective layer which electrically isolates the non-volatile memorydevice 100 and protects the non-volatile memory device 100 duringfurther processing of the integrated circuit in which the non-volatilememory device 100 is used.

The created space 10 may have any shape suitable for the specificimplementation. As shown in FIGS. 1-6, the space 10 may for example be apassage. The space 10 may for example have a first opening at a firstside of the non-volatile memory device and a second opening at a secondside of the non-volatile memory device 100. The first side and thesecond side may for example be a source side an a drain side of thenon-volatile memory device respectively.

As shown in the examples, the space 10 may be shaped as a straighttunnel with the openings facing each other. However, the space 10 mayalternatively be shaped as a recess with one or more openings at asingle side of the non-volatile memory device.

As illustrated more clearly in FIG. 2D, the space 10 may in a directionparallel to the substrate 1 be defined by walls 20,21 which arenon-parallel to the substrate 1 and extend between the openings. Thewalls 20,21 may be formed by remaining parts of the intermediate layers2,3, in this example by a remaining part of the sacrificial layer 2. Thewalls 20,21 may mechanically connect the layers above the space 10 tothe substrate 1. In this example, for instance, the control gate layer 4and the top intermediate layer 3 bridge the space 10, and aremechanically connected to the substrate 1 by the walls 20,21.

The space 10 may be defined between the first opening and the secondopening in a direction non-parallel to the substrate 1 by a side wall 11at a control gate side and a side wall 12 at a channel side (at whichthe channel 115 may be provided). The side walls may for example extendin parallel to the substrate 1. The channel side wall 12 may for examplebe formed by the substrate 1 while the control gate side wall 11 may beformed by the top intermediate layer 3 or by the control gate layer 4.The control gate side wall 11 may for example be formed by the controlgate layer 4 (as shown in FIGS. 2D and 3D), by a dielectric layer (asillustrated in FIG. 4) or by an intermediate layer 3, as is shown inFIG. 6.

Referring to FIG. 7, before, simultaneously or after the manufacturingof the non-volatile memory 100, logic devices 200 may be formed on thesame substrate 1. The formation of the logic devices 200 may includeforming a logic gate structure 205, a channel 206 which is in capacitivecontact with the logic gate structure. A gate dielectric 210 may beprovided between the logic gate structure and the channel 206. Thechannel 206 may provide a conducting path between terminals 213,214,e.g. between source and drain. The logic device 200 may for example befield effect transistor made with a silicon on nothing (SON) technique.The non-volatile memory 100 and the logic devices 200 may for example,as shown in FIG. 7, be provided as an integrated circuit including adie. The die may include a memory area with at least one non-volatilememory device is proved and a logic area with at least one logic device200.

In the foregoing specification, the invention has been described withreference to specific examples. It will, however, be evident thatvarious modifications and changes may be made therein without departingfrom the broader spirit and scope of the invention as set forth in theappended claims.

Also, for example, the substrate 1 may be a Silicon on Insulator wafer(SOI), SiGe on Insulator wafer, or Ge on Insulator (GOI) wader and/or bemade on any suitable material, such as Si, SiGe, SiC or other suitableconducting, semiconducting or insulating materials. Furthermore,although in the examples only a single memory device 100 is shown, itwill be apparent that a multiple of memory devices may be manufacturedon the same substrate, for example to manufacture a flash memory, andthat in addition to memory devices other components, such as a logiccircuit may be manufactured on the same substrate.

However, other modifications, variations and alternatives are alsopossible. The specifications and drawings are, accordingly, to beregarded in an illustrative rather than in a restrictive sense.

In the claims, any reference signs placed between parentheses shall notbe construed as limiting the claim. The word ‘comprising’ does notexclude the presence of other elements or steps then those listed in aclaim. Furthermore, the words ‘a’ and ‘an’ shall not be construed aslimited to ‘only one’, but instead are used to mean ‘at least one’, anddo not exclude a plurality. The mere fact that certain measures arerecited in mutually different claims does not indicate that acombination of these measures cannot be used to advantage.

1. A method of manufacturing a non-volatile memory device, comprising:providing at least one control gate layer (4) on a substrate; creating apassage between said at least one control gate layer and said substrate,said passage having a first opening at a first side of the non-volatilememory device and a second opening at a second side of the non-volatilememory device; providing in said passage at least one filling layer; andforming a floating gate structure including said filling layer andforming a control gate structure including said at least one controlgate layer, said control gate structure being in a stacked configurationwith said floating gate structure.
 2. A method as claimed in claim 1,wherein said passage is created between said substrate and a dielectriclayer, said dielectric layer being positioned between said substrate andsaid control gate layer.
 3. A method as claimed in claim 2, wherein saidpassage is created between said substrate and an electrically conductinglayer, which electrically conducting layer is positioned between saiddielectric layer and said substrate; and wherein said providing in saidpassage at least one filling layer comprises includes: providing atleast one dielectric layer which separates said electrically conductinglayer from a channel of the non-volatile memory device.
 4. A method asclaimed in claim 1, comprising providing in said passage at least onedielectric layer which separates a floating gate layer from said atleast one control gate layer.
 5. A method as claimed in claim 1, whereinsaid providing in said passage at least one filling layer comprises:providing in said passage at least one floating gate dielectric layer;and providing in said passage at least one floating gate layer.
 6. Amethod as claimed in claim 1, wherein at least one filling layer in afirst region is formed of a first material and in a second region isformed of a second material different from the first material.
 7. Amethod as claimed in claim 6, wherein said first region comprises: afirst gate region of a conducting material, for forming a first floatinggate and a second gate region of a conducting material, for forming asecond floating gate, and said second region includes a dielectricregion of a dielectric material which separates said first gate regionfrom said second gate region.
 8. A method as claimed in claim 7, whereinsaid dielectric material is a gas or mixture of gasses, such as air. 9.A method as claimed in claim 1, wherein: said passage is at leastdefined by a control gate side wall and a channel side wall facing thecontrol gate side wall, and said providing in said passage at least onefilling layer comprises: providing a dielectric layer on at least one ofsaid control gate side wall and said channel side wall.
 10. A method asclaimed in claim 1, wherein said channel side wall is formed by asubstrate layer.
 11. A method as claimed in claim 1, wherein saidpassage is a passage extending between a source side an a drain side ofthe non-volatile memory device.
 12. A method as claimed in claim 1,wherein said at least one control gate layer is provided on at least oneintermediate layer which separates the control gate layer from asubstrate.
 13. A method as claimed in claim 12, wherein said at leastone intermediate layer includes at least one sacrificial layer, andwherein said creating said passage includes removing said sacrificiallayer where desired.
 14. A method as claimed in claim 12, wherein saidat least one intermediate layer and/or said filling layer include one ofmore of the group consisting of: SiGe layer, Si layer, SiGeC layer,epitaxial layer, polycrystalline layer, crystalline layer.
 15. Anon-volatile memory device comprising: at least one control gate layeron a substrate; a passage between said at least one control gate layerand said substrate, said passage having a first opening at a first sideof the non-volatile memory device and a second opening at a second sideof the non-volatile memory device, in which passage at least one fillinglayer is present; and a floating gate structure including said fillinglayer and a control gate structure including said at least one controlgate layer, said control gate structure being in a stacked configurationwith said floating gate structure.
 16. An integrated circuit including adie comprising: a memory area with at least one non-volatile memorydevice as claimed in claim 15; and a logic area with at least one logicdevice.
 17. A method as claimed in claim 3, comprising providing in saidpassage at least one dielectric layer which separates a floating gatelayer from said at least one control gate layer.
 18. A method as claimedin claim 2, comprising providing in said passage at least one dielectriclayer which separates a floating gate layer from said at least onecontrol gate layer.
 19. A method as claimed in claim 2, wherein saidproviding in said passage at least one filling layer comprises:providing in said passage at least one floating gate dielectric layer;and providing in said passage at least one floating gate layer.
 20. Amethod as claimed in claim 2, wherein at least one filling layer in afirst region is formed of a first material and in a second region isformed of a second material different from the first material.